Zerocat’s Coreboot Machines  v0.10.0
How to create Zerocat’s Coreboot Machines like the ZC-X230 and others...

Main Page | Related Pages | List of Files

This file needs to get reviewed and updated. See Toolchain for most recent documentation.


This guide is about what steps are necessary to create a Zerocat Coreboot Machine. As these machines are online for sale, customers may take these notes as a reference.

Basically, a Zerocat Coreboot Machine is a Laptop which runs with a modified free coreboot firmware, holding a customized background image. Note all machines have been flashed with Zerocat’s Free-Design Chipflasher.

Available Machines

These are lists of elaborated example machines:

  1. Machines without Intel Manageability Engine (IME) hardware
    • ZC-X60, a modified ThinkPad X60 with 32bit (rarely 64bit) systemboard and up to 3.2GB RAM
    • ZC-T60, a modified ThinkPad T60 with 32bit systemboard but 64bit CPU and OS, up to 3.2GB RAM
  2. Machines with IME hardware, but its firmware update completely deleted
    • ZC-X200, a modified ThinkPad X200 with 64bit systemboard and up to 8GB RAM
    • ZC-T400, a modified ThinkPad T400 with 64bit systemboard, socketed CPU and up to 8GB RAM
  3. Machines with IME hardware, but its firmware update cleaned down to a rudimentary set
    • ZC-X220, a modified ThinkPad X220 with 64 bit system board and up to 16GB RAM
    • ZC-X230, a modified ThinkPad X230 with 64 bit system board and up to 16GB RAM
    • ZC-T430, a modified ThinkPad T430 with 64 bit system board and up to 16GB RAM
  4. Machines with IME hardware and its firmware unmodified

Basic Setup

In general, these machines come with the following software setup:

  • BIOS chip
    • proprietary Intel Manageability Engine Firmware Update deleted, stripped down, or unmodified
    • Coreboot Firmware (a fairly recent build)
      • proprietary CPU microcode updates applied
      • GRUB2 Bootloader with Authentication Support as the first Payload
      • Secondary Payloads SeaBIOS, NVRAMCUI and Coreinfo
      • proprietary VGA ROM deleted
      • customized CMOS Option Table
  • Harddisk
    • Trisquel GNU/Linux-libre Operating System, Standard Installation
      • account: trisquel
      • password: topsecret
    • Trisquel Update applied, some more Packages installed
    • On your Desktop: A backup folder of the firmware in use with the Git reference ID to Zerocat’s “Coreboot Machines” Toolchain Scripts.
    • GNU Guix Package Manager with default profile



Resource Files

General Steps

  • buy a second hand machine, check for broken hardware and missing screws
  • remove power wire and main battery pack
  • disassemble the device, get rid of proprietarily driven hardware, i.e.:
    • internal WLAN card
    • internal WWAN card
    • internal Turbo Memory card
  • locate and identify type of BIOS chip
  • attach test clip or solder wires
  • get your host ready, attach the Zerocat Chipflasher and backup the original firmware of your machine
  • deal with binary blobs:
    • extract vendor’s VGA ROM from memory while running vendor’s BIOS
    • extract important binary blobs from original firmware image (most machines) for later use
    • or generate a modified flash descriptor file (small set of machines only)
  • build your coreboot ROM image according to next section 'Roadmap to your Coreboot ROM'
  • flash and verify your coreboot image
  • reassemble the device temporarily and test for boot
  • upgrade with WLAN card, compatible to linux-libre free software drivers
  • insert harddisk or SSD
  • final assemblage
  • start from USB Live System and install the Trisquel operating system
  • check kernel ringbuffer messages for errors and/or warnings
  • perform a stress test for five minutes while observing CPU temperature
  • check S3-suspend-resume cycles for at least 3 times
  • clone the coreboot project, check coreboot buffer messages for errors and/or warnings with the cbmem tool, located in util/cbmem/

Roadmap to your Coreboot ROM

In order to generate a complete coreboot.rom for your ThinkPad’s BIOS chip, several steps are required:

This guide is using 8MB images as default, please adapt to your specific BIOS chip.
  • with GRUB, build an executable grub2.elf file...
    • with keyboard layouts
    • with fonts
  • set up your custom grub.cfg
  • deal with binary blobs:
    • with coreboot’s ifdtool, extract flashregions for later use (most machines)
    • extract vendor’s VGA BIOS (try bios_extract and UEFITool)
    • or extract vendor’s VGA BIOS while running vendor BIOS (some machines)
    • with libreboot, generate a new descriptor file with the correct MAC address and without IME firmware (i.e. ThinkPad X200, T400, T500, etc.)
  • with coreboot, build the coreboot.rom
    • with CMOS for configuration, not initialized on each startup
    • with your previously built executable payload file (i.e. grub2.elf)
  • SeaBIOS, clone, checkout, configure and build
  • add more files to the coreboot.rom
    • your custom grub.cfg
      • which will be used by the previously build grub2.elf
      • which points to your custom background.png
    • your custom background.png
    • SeaBIOS bios.bin.elf payload file and vgabios.bin option rom (if needed)
    • previously extracted flashregions / your new descriptor file
  • modify parameters in the ROM’s cmos.default with coreboot’s nvramtool, i.e.:
    • gfx_uma_size=64M
    • bluetooth=Disable
    • wwan=Disable

Once you have your coreboot.rom available, you may use...

Projects In Use

Elaborated Coreboot Build How-Tos

CMOS Checksum Reset Required

If you are updating an old coreboot image, make sure a CMOS initialization is forced.
See Remind CMOS Checksum Reset to verify our experience.

External References

Kevin Keijzer provides his valuable coreboot settings and even a dedicated bash script for your reference:

The bash script automates the steps you take after compiling a ROM (like ich9gen, adding grub.cfg, cmos settings, etc.).


The files that ship with Zerocat’s Coreboot Machines Documentation may fall into five categories:

  1. hardware design sources (files from gEDA-gschem, PCB-Designer, OpenSCAD, LibreCAD, etc.)
  2. code sources (text files with syntax of C, ASM, Makefile, Propeller-Load Configuration, Doxyfile, bash, scheme, etc.)
  3. documentation files (markdown, simple text)
  4. graphics and photos (files made with Scribus, Inkscape, Gimp, etc.)
  5. logo files (files made with Scribus, Inkscape, Gimp, etc.)

In general the following rules apply:

  • If not otherwise stated within this project, all files are copyrighted:
    Copyright (C) 2017-2019 Kai Mertens <>
  • A license header is placed within the files if applicable.
  • "1. hardware design sources" and "2. code sources" are licensed under the GNU GPLv3 or later.
    The license itself is shipped as COPYING.
  • "3. documentation files" are licensed under GNU FDL 1.3 or later, without invariant sections, front-cover texts or back-cover texts.
    This license is shipped with COPYING-DOCUMENTATION.
  • "4. graphics and photos" are released under the CC BY-SA 4.0 International Public License.
    The URL to the license text is shipped with COPYING-GRAPHICS.
  • "5. logo files" are released under the Zerocat Logo License.
    This license is shipped with COPYING-LOGO.

Main Page | Related Pages | List of Files